IRDS 主席Paolo A. Gargini博士到访微纳电子学系
2019年6月22日，来自英特尔公司的国际半导体器件与系统技术路线组织（IRDS）主席、国际电子电器工程师协会（IEEE）会士、日本应用物理协会（JSAP）会士，Paolo A. Gargini博士应邀到访微纳电子学系，参观了我系微米纳米国家级重点实验室，并在微纳电子大厦103报告厅做了题为《How to Successfully Overcome Inflection Points by using the Technology Roadmap Methodology》的精彩学术报告。微纳电子学系多位老师以及研究生、本科生参加了报告会，并与报告人进行了热烈的讨论。
How to Successfully Overcome Inflection Points by using the Technology Roadmap Methodology
Geometrical Scaling” characterized the 70’s, 80’s and 90’s. The NTRS identified major transistors material and structural limitations. To solve these problems the ITRS introduced strained silicon, high-κ/metal gate, FinFET, and other semiconductor materials under “Equivalent Scaling”.
Horizontal (2D) features will reach a limit beyond 2020. Flash producers have adopted the vertical dimension. Logic producers will follow. IRDS assessed that “3D Power Scaling” will extend Moore’s Law for at least another 15 years. Furthermore, computing performance will be substantially improved by monolithically integrating several new heterogeneous memory layers on top of logic layers powered by a combination of CMOS and “new switch” transistors.